1. Field of the Invention
This invention relates in general to a methodology to improve the packaging and distribution of power to electronic circuits, and also provides efficient means to purge any excess associated heat from such electronic assemblies. The present invention addresses these issues by encapsulating the circuitry within a circuit board structure which improves power distribution, thermal, mechanical and integrated circuit device management over existing technologies known in the art today.
2. Description of Related Art
As circuitry in electronics becomes more complex, packaging of the circuitry has become more difficult. The common method for packaging integrated circuits and other electronic components is to mount them on Printed Circuit Boards (PCBs).
Recently, the application of new organic laminates in the construction of Multi-Chip-Modules (MCMs) has brought about significant improvements in the packaging cost and density of electronic circuits. The circuit density of electronic circuits on silicon and other semiconductor materials continues to increase, along with an increase in the overall size of the semiconductor chip. This increase in density causes the total power level of many electronic chips to increase even though the operating voltage levels have decreased due to improvements in process fabrication. The net result has been a significant problem associated with the delivery of power to these devices.
Computer chip clocking speeds have also increased. This increase in speed has made it difficult to couple chips together in such a way that the internal chip speeds are completely useable, i.e., the I/O for a given chip typically cannot keep up with the internal chip speeds. Further, heat generated by integrated circuits has increased because of the increased speed and increased number of signals travelling through the integrated circuits. In addition, as die sizes increase interconnect delays on the dies are beginning to limit the circuit speeds within the dies. Typically, the limitations of a system are contributed to, in part, by the packaging of the system itself. These effects are forcing greater attention to methods of efficiently coupling and integrating high-speed integrated circuits.
Packaging the integrated circuits onto PCBs has become increasingly more difficult because of the signal density within integrated circuits and the requirements of power distribution and heat dissipation. Typical interconnections on a PCB are made using traces that are etched or pattern plated onto conductive layers of the PCB. To create shorter interconnections, Surface Mount Technology (SMT) chips, Very Large Scale Integration (VLSI) circuits, flip chip bonding, Application Specific Integrated Circuits (ASICs), Ball Grid Arrays (BGAs), and the like, have been used to shorten the transit time and interconnection lengths between chips on a PCB. However, this technology has not completely overcome the needs for higher signal speeds in both intra-PCB and inter-PCB structures because of power distribution considerations, thermal considerations, EMI concerns, and other packaging related problems.
In any given system, PCB area (also known as PCB xe2x80x9creal estatexe2x80x9d) is at a premium. With smaller packaging envelopes becoming the norm in electronics, e.g., laptop computers, spacecraft, cellular telephones, etc., large PCBs are not available for use to mount SMT chips, BGAs, flip chips or other devices. Newer methods are emerging to decrease the size of PCBs such as build-up-multilayer technology, improved organic laminate materials with reduced thicknesses and dielectric constants, and laser beam photo imaging. These technologies produce greater pressure to maintain the functionality of the PCB assembly through power, thermal, and Electromagnetic Interference (EMI) management to the semiconductor devices.
It can be seen, then, that there is a need in the art for a method for decreasing the size of PCBs while maintaining the functionality of PCBs. Further, there is a need for reducing the size of PCBs while using present-day manufacturing techniques to maintain low cost packaging. It can also be seen that there is a need in the art for techniques to deliver power to devices without degrading the performance of the overall system.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses an encapsulated circuit assembly which utilizes printed circuit boards as a foundation for the assembly structure. The assembly comprises a first printed circuit board, a second printed circuit board, and a mechanical coupler. The mechanical coupler is coupled between the first printed circuit board and the second printed circuit board and disposed between the first printed circuit board and the second printed circuit board. The mechanical coupler provides substantial electrical continuity between a trace on the first printed circuit board and a trace on the second printed circuit board.
An object of the present invention is to provide method for decreasing the size of PCBs while maintaining the functionality of PCBs. Another object of the invention is to improve the distribution of high power and low voltage to integrated circuit assemblies. Another object of the present invention is to provide techniques to deliver power to devices without degrading the performance of the overall system.
These and various other advantages and features of novelty that characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to the accompanying detailed description, in which there is illustrated and described specific examples of methods and apparatuses in accordance with the invention.